EDA Characterization Engineer (Chip-Design Software Startup)

An early-stage company applying machine learning to chip layout and optimization needs a specialist to create its library characterization technology from a blank page. The team is small and technically deep, drawn from electronic design automation and ML backgrounds, and this person will own a core piece of infrastructure from start to finish.

Scope

• Architect and implement a fast, scalable engine that generates delay, power and noise views for library cells plus bespoke IP, targeting NLDM, CCS and ECSM formats
• Build the orchestration layer around circuit simulation: scheduling, parallel execution and smart sampling that shortens run time while keeping accuracy intact
• Take charge of Liberty file generation, along with the checks confirming results are usable in downstream static timing analysis
• Work out with the optimization and ML groups which characterization inputs they require, then expose them through programmatic interfaces
• Weigh speed against fidelity and justify those decisions to demanding technical customers

Ideal background

• Three to ten years constructing characterization tools or doing EDA R&D, working in C++ and Python
• You have built or extended such tooling at a commercial EDA vendor or on an internal CAD team at a semiconductor company, rather than only operating it
• Solid command of characterization methodology and SPICE-level simulation (HSPICE, Spectre or FineSim)
• Master’s or PhD in electrical engineering, computer science or a related area; a bachelor’s plus strong hands-on tool-building can also work
• Plus: surrogate modeling or ML to accelerate characterization

Hybrid in the San Francisco Bay Area. Visa transfers and new visa sponsorship are both available.